Added interrupt and exception handling
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166
idt.c
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166
idt.c
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#include "idt.h"
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#define IDT_SIZE 256
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#define IDT_TYPE_INTERRUPT 0x8E
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typedef struct {
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UINT16 offset_low;
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UINT16 selector;
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UINT8 ist;
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UINT8 type_attr;
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UINT16 offset_mid;
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UINT32 offset_high;
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UINT32 zero;
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} __attribute__((packed)) IdtEntry;
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typedef struct {
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UINT16 limit;
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UINT64 base;
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} __attribute__((packed)) IdtPtr;
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static IdtEntry idt[IDT_SIZE];
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static BootInfo *gBoot = NULL;
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extern void (*isr_stub_table[])(void);
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static void idt_set_gate(UINTN index, void (*handler)(void))
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{
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UINT64 addr = (UINT64)(UINTN)handler;
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UINT16 selector = 0;
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__asm__ __volatile__("mov %%cs, %0" : "=r"(selector));
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idt[index].offset_low = (UINT16)(addr & 0xFFFF);
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idt[index].selector = selector;
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idt[index].ist = 0;
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idt[index].type_attr = IDT_TYPE_INTERRUPT;
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idt[index].offset_mid = (UINT16)((addr >> 16) & 0xFFFF);
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idt[index].offset_high = (UINT32)((addr >> 32) & 0xFFFFFFFF);
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idt[index].zero = 0;
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}
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static void lidt(const IdtPtr *idtr)
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{
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__asm__ __volatile__("lidt (%0)" :: "r"(idtr));
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}
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static const CHAR16 *exception_name(UINTN vector)
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{
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switch (vector) {
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case 0: return L"Divide Error";
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case 1: return L"Debug";
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case 2: return L"Non-Maskable Interrupt";
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case 3: return L"Breakpoint";
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case 4: return L"Overflow";
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case 5: return L"Bound Range Exceeded";
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case 6: return L"Invalid Opcode";
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case 7: return L"Device Not Available";
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case 8: return L"Double Fault";
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case 9: return L"Coprocessor Segment Overrun";
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case 10: return L"Invalid TSS";
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case 11: return L"Segment Not Present";
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case 12: return L"Stack-Segment Fault";
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case 13: return L"General Protection Fault";
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case 14: return L"Page Fault";
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case 15: return L"Reserved";
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case 16: return L"x87 Floating-Point";
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case 17: return L"Alignment Check";
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case 18: return L"Machine Check";
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case 19: return L"SIMD Floating-Point";
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case 20: return L"Virtualization";
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case 21: return L"Control Protection";
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case 22: return L"Reserved";
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case 23: return L"Reserved";
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case 24: return L"Reserved";
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case 25: return L"Reserved";
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case 26: return L"Reserved";
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case 27: return L"Reserved";
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case 28: return L"Hypervisor Injection";
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case 29: return L"VMM Communication";
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case 30: return L"Security";
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case 31: return L"Reserved";
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default: return L"Unknown";
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}
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}
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static inline void outb(UINT16 port, UINT8 value)
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{
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__asm__ __volatile__("outb %0, %1" :: "a"(value), "Nd"(port));
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}
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static void pic_eoi(UINTN vector)
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{
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if (vector >= 40) {
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outb(0xA0, 0x20); /* EOI to slave PIC */
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}
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outb(0x20, 0x20); /* EOI to master PIC */
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}
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static void halt_forever(void)
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{
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for (;;) {
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__asm__ __volatile__("cli; hlt");
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}
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}
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void isr_handler(ISRFrame *frame)
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{
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UINT64 cr2 = 0;
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/* Hardware IRQs (vectors 32-47): send EOI and return */
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if (frame->vector >= 32 && frame->vector <= 47) {
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pic_eoi(frame->vector);
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return;
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}
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/* CPU exceptions (vectors 0-31): print diagnostics and halt */
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if (gBoot != NULL && gBoot->print != NULL) {
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gBoot->print(L"\n\rEXCEPTION: %d (%s)\n\r", frame->vector,
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exception_name(frame->vector));
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gBoot->print(L" Error Code: 0x%lx\n\r", frame->error_code);
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gBoot->print(L" RIP: 0x%lx CS: 0x%lx RFLAGS: 0x%lx\n\r",
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frame->rip, frame->cs, frame->rflags);
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}
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if (frame->vector == 14) {
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__asm__ __volatile__("mov %%cr2, %0" : "=r"(cr2));
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if (gBoot != NULL && gBoot->print != NULL) {
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gBoot->print(L" CR2: 0x%lx\n\r", cr2);
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}
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}
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halt_forever();
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}
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void idt_init(BootInfo *Boot)
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{
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IdtPtr old_idtr;
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IdtPtr idtr;
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IdtEntry *old_idt = NULL;
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UINTN i = 0;
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gBoot = Boot;
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/* Read the firmware's existing IDT so we can preserve its entries */
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__asm__ __volatile__("sidt %0" : "=m"(old_idtr));
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old_idt = (IdtEntry *)(UINTN)old_idtr.base;
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/* Copy the entire existing IDT first (preserves firmware IRQ handlers) */
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for (i = 0; i < IDT_SIZE; i++) {
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if (old_idt != NULL && (i * sizeof(IdtEntry)) < (UINTN)(old_idtr.limit + 1)) {
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idt[i] = old_idt[i];
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} else {
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idt_set_gate(i, isr_stub_table[i]);
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}
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}
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/* Override only CPU exception vectors (0-31) with our handlers */
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for (i = 0; i < 32; i++) {
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idt_set_gate(i, isr_stub_table[i]);
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}
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idtr.limit = (UINT16)(sizeof(idt) - 1);
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idtr.base = (UINT64)(UINTN)idt;
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lidt(&idtr);
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}
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